Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a control circuit for controlling a digital circuit included in an integrated circuit and method for driving the control circuit.
FIG. 1 illustrates a block diagram for a conventional integrated circuit.
Referring to FIG. 1, an integrated circuit 100 includes a digital counter 110, a digital circuit 120, and an alignment unit 130. The digital counter 110 receives an enable signal EN, synchronizes the enable signal EN with a clock signal CLK, and outputs a count code value CNT_OUT<0:N>. The digital circuit 120 receives the count code value CNT_OUT<0:N> from the digital counter 110 and when the count code value CNT_OUT<0:N> is equal to a target value, performs a designated operation. The alignment unit 130 latches a digital signal DGT_OUT<0:M>, which is outputted from the digital circuit 120, synchronizes the digital signal DGT_OUT<0:M> with the clock signal CLK and outputs a final digital signal FDGT_OUT<0:M>.
Here, the digital counter 110 and the alignment unit 130 are synchronous circuits synchronized with the clock signal CLK, while the digital circuit 120 is a circuit that is not synchronized with the clock signal CLK.
An operation of the integrated circuit 100 is described follows.
FIG. 2 illustrates a timing diagram for illustrating the operation of the integrated circuit 100.
Hereinafter, the target value may be “3”. When the count code value CNT_OUT<0:N> is equal to the target value “3”, the digital circuit 120 performs the designated operation and outputs the digital signal DGT_OUT<0:M>.
Referring to FIG. 2, the digital counter 110 is responsive to the enable signal EN (as shown in FIG. 1), performs a count operation in synchronization with a rising edge of the clock signal CLK and outputs the count code value CNT_OUT<0:N>, which is counted in sequence. If the count code value CNT_OUT<0:N> is a 4-bit signal, the digital counter 110 will output a logical combination of 4-bit count code value CNT_OUT<0:3> to indicate a designated count value. For example, the digital counter 110 will output the count code value CNT_OUT<0:3> of “0000” to indicate a count value “0” and will output the count code value CNT_OUT<0:3> of “0011” to indicate a count value “3”. Here, the count code value CNT_OUT<0:N> is delayed and outputted later than the rising edge of the clock signal CLK by a first delay time T1.
The digital circuit 120 receives the count code value CNT_OUT<0:N> from the digital counter 110 and when the count code value CNT_OUT<0:N> is equal to the target value “3”, performs the intended operation and outputs the digital signal DGT_OUT<0:M>. The digital signal DGT_OUT<0:M> is delayed and outputted later than the count code value CNT_OUT<0:N> by a second delay time T2. Further, a setup margin time Tsetup exists between the digital signal DGT_OUT<0:M> and the clock signal CLK.
The alignment unit 130 aligns the digital signal DGT_OUT<0:M>, which is outputted from the digital circuit 120, and outputs the final digital signal FDGT_OUT<0:M> in synchronization with the clock signal CLK.
The conventional integrated circuit 100 has the following features.
Before describing the features of the conventional integrated circuit 100, a timing error will be described. The count code value CNT_OUT<0:N> is outputted in synchronization with a first rising edge R1 of the clock signal CLK, while the final digital signal FDGT_OUT<0:M> is outputted in synchronization with a second rising edge R2 of the clock signal CLK. That is, the clock edge R1 for outputting the count code value<0:N> corresponding to the target count value “3” is different from the clock edge R2 for outputting the final digital signal FDGT_OUT<0:M>, and an interval between the clock edge R1 and the clock edge R2 is equal to 1tCK, which is a period of the clock signal CLK. It is the result of the first delay time T1, the second delay time T2 and the setup margin time Tsetup. A total time of the first delay time T1, the second delay time T2 and the setup margin time Tsetup is less than the period of the clock signal CLK, i.e., 1tCK. Here, during a signal transmission, a signal delay is generated, and a timing difference between a signal input and a signal output is referred to as a timing error. For example, due to the timing error, the count code value CNT_OUT<0:N> corresponding to the target count value “3” is inputted at the first clock edge R1, and the final digital signal FDGT_OUT<0:M> is outputted at the second clock edge R2. At this time, if the values of the first delay time T1, the second delay time T2, and the setup margin time Tsetup are not changed, a timing interval between the timing (that is, first clock edge R1) for inputting the count code value CNT_OUT<0:N> corresponding to the target count value “3” and the timing (that is, the second clock edge R2) for outputting the final digital signal FDGT_OUT<0:M> will be the period of the clock signal CLK, i.e. 1tCK. Here, if the values of the first delay time T1, the second delay time T2 and the setup margin time Tsetup are not changed, the timing interval between a signal input timing and a signal output timing is known, such a timing error is not significant.
However, the first delay time T1, the second delay time T2 and the setup margin time Tsetup vary, as conditions of process (P), voltage (V), and temperature (T) are varied. Particularly, because the digital circuit 120 as the asynchronous circuit is susceptible of the PVT condition, it is difficult to predict a variation of the second delay time T2, which is generated during the operation of the digital circuit 120. On some occasions, as the first delay time T1, the second delay time T2 and the setup margin time Tsetup all vary, the total time of the first delay time T1, the second delay time T2 and the setup margin time Tsetup may be greater than the period of the clock signal CLK. This occasion is illustrated in FIG. 3. Referring FIG. 3, the total time of the first delay time T1, the second delay time T2 and the setup margin time Tsetup is greater than the period of the clock signal CLK. Consequently, the final digital signal FDGT_OUT<0:M> is outputted in synchronization with not the second edge R2 of the clock signal CLK, but a third edge R3 of the clock signal CLK.
As such, when it is difficult to predict the timing error according to the variations of the PVT conditions, the integrated circuit 100 will be deteriorated in terms of operation reliability. Particularly, timing errors increase in magnitude, as a frequency of the clock signal CLK becomes higher to achieve high speed operations of the integrated circuit 100.
As an attempt to address the above described features with respect to operation reliability, an integrated circuit 200 in FIGS. 4 and 5 has been proposed. An integrated circuit 200 includes a delay replica unit 240, which delays the clock signal CLK by the total time of the first delay time T1, the second delay time T2 and the setup margin time Tsetup, and provides the delayed clock signal CLK_DELY with the alignment unit 130. The delay replica unit 240 is a replica element that somewhat reflects the variation of the first delay time T1, the second delay time T2 and the setup margin time Tsetup in the real path through the digital counter 110, the digital circuit 120 and the alignment unit 130 in generating the delayed clock signal CLK_DELY. However, it is difficult to implement the delay replica unit 240. Further, if the delay replica unit 240 is embodied as a circuit identical to the real path, the size of the circuit will be large and power consumption increases.